The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

May. 30, 2013
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Bhavesh Davda, Fremont, CA (US);

Benjamin Charles Serebrin, Sunnyvale, CA (US);

Assignee:

VMware, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 12/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1081 (2013.01); G06F 13/28 (2013.01); G06F 2212/1024 (2013.01);
Abstract

Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing, in a first memory, data to be transmitted. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to retrieve, for transmission, first data from a first buffer indexed by a first descriptor in the ring of descriptors and before second data is determined to be ready for transmission, the first address translation being associated with a second DMA operation for retrieving the second data from the first memory.


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