The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2016
Filed:
Nov. 29, 2012
Ravindraraj Ramaraju, Round Rock, TX (US);
Jianan Yang, Austin, TX (US);
Mark W. Jetton, Austin, TX (US);
Thomas W. Liston, Austin, TX (US);
George P. Hoekstra, Austin, TX (US);
Andrew C. Russell, Austin, TX (US);
Ravindraraj Ramaraju, Round Rock, TX (US);
Jianan Yang, Austin, TX (US);
Mark W. Jetton, Austin, TX (US);
Thomas W. Liston, Austin, TX (US);
George P. Hoekstra, Austin, TX (US);
Andrew C. Russell, Austin, TX (US);
Other;
Abstract
In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.