The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9312868 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 12, 2016

Filed:

Nov. 08, 2013
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Dae-Suk Kim, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/197 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1978 (2013.01);
Abstract

A semiconductor device includes a buffer suitable for receiving an input signal, a clock buffer suitable for receiving a clock, a delay locked loop (DLL) suitable for delaying the clock to generate a delay locked clock, a code generation unit suitable for generating a digital code corresponding to 1/N of the clock cycle where N is an integer equal to or more than two, a delay unit suitable for delaying the clock corrected by the DLL by a value corresponding to the digital code to output a delayed clock, and a strobing unit suitable for strobing the input signal using the delayed clock.


Find Patent Forward Citations

Kim, Dae-Suk. (2016). Clock phase adjusting circuit and semiconductor device including the same (U.S. Patent No. 9312868). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9312868

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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