The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Jun. 25, 2015
Applicant:

Tianjin Sanan Optoelectronics Co., Ltd., Tianjin, CN;

Inventors:

Li-Ming Shu, Tianjin, CN;

Xiao-Feng Liu, Tianjin, CN;

Dong-Yan Zhang, Tianjin, CN;

Ming-Ying Liu, Tianjin, CN;

Liang-Jun Wang, Tianjin, CN;

Du-Xiang Wang, Tianjin, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/46 (2010.01); H01L 21/00 (2006.01); H01L 33/06 (2010.01); H01L 33/00 (2010.01); H01L 33/32 (2010.01); H01L 33/14 (2010.01); H01L 33/24 (2010.01); H01L 33/30 (2010.01); H01L 33/02 (2010.01); H01L 33/22 (2010.01); H01L 33/12 (2010.01);
U.S. Cl.
CPC ...
H01L 33/06 (2013.01); H01L 33/0075 (2013.01); H01L 33/025 (2013.01); H01L 33/12 (2013.01); H01L 33/145 (2013.01); H01L 33/22 (2013.01); H01L 33/24 (2013.01); H01L 33/30 (2013.01); H01L 33/32 (2013.01);
Abstract

A LED fabrication method includes: providing a substrate; forming a low-temperature AlGaN (0≦x≦1) layer over the growth substrate; setting the growth pressure from high to low and temperature and rotation rate from low to high to realize change from three-dimensional growth to two-dimensional growth of the GaN structure layer before growth of the multiple quantum-well layer, in which, Si is doped at position approximate to the multiple quantum-well layer to form an undoped gradient GaN layer and an N-type gradient GaN layer; growing a multiple quantum-well layer, an AlGaN (0≦x≦1) layer and a P-type layer; and during later chip fabrication, dividing the epitaxial wafer over the etched N-type platform into chip grains and immersing them in chemical solutions for wet etching; and forming an inverted pyramid structure with rough side wall over the multiple quantum-well layer to improve light-emitting efficiency.


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