The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Mar. 03, 2015
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Hiroaki Yamashita, Hakusan Ishikawa, JP;

Syotaro Ono, Kanazawa Ishikawa, JP;

Hideyuki Ura, Hakusan Ishikawa, JP;

Masaru Izumisawa, Kanazawa Ishikawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/76 (2006.01); H01L 27/088 (2006.01); H01L 27/06 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 29/0684 (2013.01); H01L 29/4236 (2013.01); H01L 29/66348 (2013.01); H01L 29/66734 (2013.01); H01L 29/7397 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided in the first semiconductor region, an element region, and a termination region. The element region includes a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, and a gate electrode disposed on a gate insulating layer that extends adjacent the third semiconductor region and the fourth semiconductor region. The termination region surrounds the element region and includes a first electrode, which includes first portions extending in a first direction and second portions extending in a second direction. A plurality of first electrodes are provided on the first semiconductor region and the second semiconductor region. An interval between adjacent first portions in the second direction is less than an interval between adjacent second portions in the first direction.


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