The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Nov. 27, 2013
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Karl R. Erickson, Rochester, MN (US);

Phil C. Paone, Rochester, MN (US);

David P. Paulsen, Dodge Center, MN (US);

John E. Sheets, II, Zumbrota, MN (US);

Gregory J. Uhlmann, Rochester, MN (US);

Kelly L. Williams, Rochester, MN (US);

Assignee:

Globalfoundries Inc., Ugland House, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 27/06 (2006.01); G06F 17/50 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/845 (2013.01); H01L 27/0688 (2013.01); H01L 27/1211 (2013.01); G06F 17/5068 (2013.01); H01L 27/0886 (2013.01);
Abstract

A method and circuit for implementing an enhanced transistor topology with a buried field effect transistor (FET) utilizing the drain of a FinFET as the gate of the new buried FET and a design structure on which the subject circuit resides are provided. A drain area of the fin area of a FinFET over a buried dielectric layer provides both the drain of the FinFET as well as the gate node of a second field effect transistor. This second field effect transistor is buried in the carrier semiconductor substrate under the buried dielectric layer.


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