The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Oct. 15, 2013
Applicant:

Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;

Inventors:

Naoki Ueda, Osaka, JP;

Sumio Katoh, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 27/112 (2006.01); H01L 27/10 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); G11C 13/003 (2013.01); G11C 13/0007 (2013.01); H01L 27/101 (2013.01); G11C 13/0069 (2013.01); G11C 2213/53 (2013.01); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01);
Abstract

The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without receiving an influence of deterioration of a selection transistor connected in series to the memory transistor. A memory cellincludes a memory transistor Qm, and first and second selection transistors Qand Q. During a writing operation, the memory transistor Qm and the first selection transistor Qare set to the ON state, and the second selection transistor Qis set to the OFF state. A writing current is flown to a series circuit of the memory transistor Qm and the first selection transistor Q. The memory transistor Qm is transited from a first state that indicates a transistor characteristic to a second state that indicates an ohmic resistance characteristic. During a reading operation, the first selection transistor Qis set to the OFF state, the second selection transistor Qis set to the ON state, a voltage is applied to a series circuit of the memory transistor Qm and the second selection transistor Q, and it is detected whether the memory transistor Qm is in the first state or the second state.


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