The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

May. 06, 2014
Applicant:

Spansion Llc, Sunnyvale, CA (US);

Inventor:

Masanori Onodera, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/03 (2006.01); H01L 25/10 (2006.01); H01L 23/02 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/56 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 25/03 (2013.01); H01L 25/105 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/48 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1052 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/078 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19107 (2013.01);
Abstract

A semiconductor deviceincludes: a first semiconductor package; a first interposerhaving an upper surface on which the first semiconductor packageis mounted; a first molding resinthat is provided on the upper surface of the first interposerand seals the first semiconductor package; a second semiconductor packagemounted on an upper surface of the first molding resin; a second interposeron which the second semiconductor packageis mounted by flip chip bonding; and a second molding resinthat is provided on the upper surface of the first interposerand seals the first molding resin, the second semiconductor package, and the second interposer. The second semiconductor packageis mounted, with a surface thereof opposite to another surface mounted on the second interposerfaced down, on the upper surface of the first molding resinvia an adhesive


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