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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9312209 B1

PDFFull Text
Date of Patent:
Apr. 12, 2016

Filed:

Feb. 27, 2015

Semiconductor device

Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventors:

Kayoko Shibata, Tokyo, JP;

Hitoshi Miwa, Kokubunji, JP;

Yoshihiko Inoue, Kokubunji, JP;

Assignee:

PS4 LUXCO S.A.R.L., Luxembourg, LU;

Attorney:

Kunzler Law Group

Primary Examiner:

Brian Ngo

Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01); H01L 23/48 (2006.01); G11C 5/06 (2006.01); G11C 29/02 (2006.01); G11C 29/12 (2006.01); H01L 25/065 (2006.01); H01L 27/108 (2006.01); H01L 23/538 (2006.01); H01L 27/105 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); G11C 5/063 (2013.01); G11C 29/025 (2013.01); G11C 29/12 (2013.01); G11C 29/1201 (2013.01); H01L 23/5384 (2013.01); H01L 25/0657 (2013.01); H01L 27/1052 (2013.01); H01L 27/10897 (2013.01); H01L 22/22 (2013.01); H01L 2224/16145 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01037 (2013.01); H01L 2924/01055 (2013.01);
Abstract

A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n−x switch circuits to connect n−x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

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