The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2016
Filed:
Mar. 07, 2014
Tea-kwang Yu, Hwaseong-si, KR;
Bae-seong Kwon, Bucheon-si, KR;
Yong-tae Kim, Yongin-si, KR;
Chul-ho Chung, Hwaseong-si, KR;
Yong-suk Choi, Hwaseong-si, KR;
Tea-Kwang Yu, Hwaseong-si, KR;
Bae-Seong Kwon, Bucheon-si, KR;
Yong-Tae Kim, Yongin-si, KR;
Chul-Ho Chung, Hwaseong-si, KR;
Yong-Suk Choi, Hwaseong-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do, KR;
Abstract
In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.