The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Jun. 11, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Daniel Nelson Carothers, Lucas, TX (US);

Jeffrey R. Debord, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/762 (2013.01); H01L 21/0223 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02647 (2013.01); H01L 21/02667 (2013.01); H01L 21/30625 (2013.01); H01L 21/0262 (2013.01); H01L 21/02255 (2013.01); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01);
Abstract

An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa. A cap layer is formed over the second epitaxial layer, and a radiantly-induced recrystallization process causes the non-crystalline silicon-based material to form single-crystalline semiconductor over the isolation mesa.


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