The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Nov. 01, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Yongkyu Lee, Gyeonggi-do, KR;

Sungyeon Lee, Seoul, KR;

Yeongtaek Lee, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/56 (2006.01); G11C 29/50 (2006.01); G11C 29/52 (2006.01); G11C 7/10 (2006.01); G11C 8/16 (2006.01); G11C 11/00 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 7/1075 (2013.01); G11C 8/16 (2013.01); G11C 11/005 (2013.01); G11C 11/5607 (2013.01); G11C 11/5614 (2013.01); G11C 11/5642 (2013.01); G11C 11/5657 (2013.01); G11C 11/5678 (2013.01); G11C 29/50008 (2013.01); G11C 29/52 (2013.01); G11C 2013/0054 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 2213/72 (2013.01);
Abstract

A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line. One of the first sink transistors is disposed between one end of the row line and a ground and the other of the first sink transistors is disposed between an opposite end of the row line and the ground. One of the second sink transistors is disposed between one end of the reference row line and the ground and the other of the second sink transistors is disposed between an opposite end of the reference row line and the ground. The word line is coupled to gates of the first and second sink transistors.


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