The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2016
Filed:
Jun. 14, 2013
National Instruments Corporation, Austin, TX (US);
Craig S. Jones, Austin, TX (US);
Jonathan W. Hearn, Austin, TX (US);
Jason D. Tongen, Austin, TX (US);
National Instruments Corporation, Austin, TX (US);
Abstract
A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information.