The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Apr. 15, 2014
Applicants:

Carl Culshaw, Wigan, GB;

Mark Maiolani, Glasgow, GB;

Robert F. Moran, Largs, GB;

Inventors:

Carl Culshaw, Wigan, GB;

Mark Maiolani, Glasgow, GB;

Robert F. Moran, Largs, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G06F 11/30 (2006.01); G11C 29/42 (2006.01); G11C 29/02 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3027 (2013.01); G11C 29/022 (2013.01); G11C 29/42 (2013.01); G11C 2029/0409 (2013.01);
Abstract

An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit.


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