The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2016
Filed:
May. 06, 2012
Cosmin Iorga, Newbury Park, CA (US);
Cosmin Iorga, Newbury Park, CA (US);
Other;
Abstract
On-die measurement of power distribution impedance frequency profile of a programmable logic device (PLD), such as field programmable gate array (FPGA) or complex programmable logic device (CPLD), is performed by configuring and using only logic blocks resources commonly available in any existing programmable logic device, without the need of built-in dedicated circuits. All measurements are done inside the programmable logic device without the need of external instruments. The measurement method can be used during characterization to select decoupling capacitors or for troubleshooting existing systems, after which the programmable logic device may be reconfigured to perform any other user-defined function.