The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Sep. 30, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Phaedon Avouris, Yorktown Heights, NY (US);

Michael Engel, Ossining, NY (US);

Claudius Feger, Poughkeepsie, NY (US);

Ronaldo Giro, Rio de Janeiro, BR;

Rodrigo Ferreira, Rio de Janeiro, BR;

Mathias Steiner, Rio de Janeiro, BR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); G01N 11/04 (2006.01); H01L 29/16 (2006.01); H01L 29/49 (2006.01); G06F 17/50 (2006.01); G01N 11/00 (2006.01);
U.S. Cl.
CPC ...
G01N 11/04 (2013.01); G06F 17/5009 (2013.01); G06F 17/5068 (2013.01); H01L 29/1606 (2013.01); H01L 29/4966 (2013.01); G01N 2011/008 (2013.01);
Abstract

An Integrated Circuit (IC) chip with a lab-on-a-chip, a method of manufacturing the lab-on-a-chip and a method of using the lab-on-a-chip for fluid flow analysis in physical systems through combination with computer modeling. The lab-on-a-chip includes cavities in a channel layer and a capping layer, preferably transparent, covering the cavities. Gates control two dimensional (2D) lattice structures acting as heaters, light sources and/or sensors in the cavities, or fluid channels. The gates and two dimensional (2D) lattice structures may be at the cavity bottoms or on the capping layer. Wiring connects the gates and the 2D lattice structures externally.


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