The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Sep. 26, 2014
Applicant:

Broadcom Corporation, Irvine, CA (US);

Inventors:

Heng Zhang, Irvine, CA (US);

Mehdi Khanpour, Irvine, CA (US);

Jun Cao, Irvine, CA (US);

Chang Liu, Irvine, CA (US);

Afshin Momtaz, Laguna Hills, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/74 (2006.01); H03D 3/02 (2006.01); H03D 3/00 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04B 1/745 (2013.01); H03D 3/006 (2013.01); H03D 3/02 (2013.01); H04L 7/033 (2013.01);
Abstract

Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.


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