The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Mar. 04, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Soon Suk Hwang, Ansan-si, KR;

Youngjin Cho, Seoul, KR;

Kyuwook Han, Seoul, KR;

Jaegeun Park, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); H03L 7/08 (2006.01); H03L 7/085 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0802 (2013.01); G11C 7/22 (2013.01); H03L 7/085 (2013.01);
Abstract

A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.


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