The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Jan. 09, 2015
Applicant:

Linear Technology Corporation, Milpitas, CA (US);

Inventors:

Ciaran J. Brennan, Essex Junction, VT (US);

Mukesh Kumar, Fairfax, VT (US);

Assignee:

Linear Technology Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/00 (2006.01); H03K 5/1532 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1532 (2013.01);
Abstract

A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs. For each and every unique combination of two of the multiple inputs, the voltage selection circuit may include an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs through the channel of an additional depletion mode FET.


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