The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Jul. 27, 2012
Applicants:

Siok Wei Lim, Singapore, SG;

Cheng-hsiang Hsieh, San Jose, CA (US);

Jafar Savoj, Sunnyvale, CA (US);

Inventors:

Siok Wei Lim, Singapore, SG;

Cheng-Hsiang Hsieh, San Jose, CA (US);

Jafar Savoj, Sunnyvale, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H03F 1/52 (2006.01); H03F 3/45 (2006.01); H03F 3/72 (2006.01); H04L 27/00 (2006.01); H03H 11/12 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
H03F 1/523 (2013.01); H03F 3/45224 (2013.01); H03F 3/45233 (2013.01); H03F 3/72 (2013.01); H04L 27/0002 (2013.01); H03F 2200/444 (2013.01); H03F 2203/45091 (2013.01); H03F 2203/45092 (2013.01); H03F 2203/45466 (2013.01); H03F 2203/45494 (2013.01); H03F 2203/45568 (2013.01); H03H 11/1213 (2013.01); H04L 25/0276 (2013.01);
Abstract

In one embodiment, a differential amplifier is provided. Gates of a first differential pair of transistors, of a first conductivity type, and a second pair or transistors, of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.


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