The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Apr. 02, 2015
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventor:

Chien-Hui Chuang, New Taipei, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H02H 9/04 (2006.01); H01L 27/02 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H02H 9/04 (2013.01); H01L 27/0266 (2013.01); H01L 27/0277 (2013.01); H03K 19/00315 (2013.01);
Abstract

An electrostatic discharge protection circuit is provided. First NMOS transistor is coupled to a power line. Second NMOS transistor is coupled between the first NMOS transistor and a ground. Detection unit provides a detection signal when an ESD event occurs at the power line. Trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal. Discharge path is formed from the power line to the ground via the first and second NMOS transistors. First PMOS transistor is coupled between the power line and a gate of the second NMOS transistor. Third NMOS transistor is coupled between the ground and the gate of the second NMOS transistor. Second PMOS transistor is coupled between the gates of the first and second NMOS transistors. Third PMOS transistor is coupled between the power line and the first PMOS transistor.


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