The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Jun. 16, 2011
Applicants:

Shuxian Chen, Fremont, CA (US);

Jeffrey T. Watt, Palo Alto, CA (US);

Inventors:

Shuxian Chen, Fremont, CA (US);

Jeffrey T. Watt, Palo Alto, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01F 17/00 (2006.01);
U.S. Cl.
CPC ...
H01L 28/10 (2013.01); H01F 17/0013 (2013.01); H01L 23/5227 (2013.01); H01F 2017/0046 (2013.01); H01F 2017/0073 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance.


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