The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Aug. 13, 2015
Applicant:

Omnivision Technologies, Inc., Santa Clara, CA (US);

Inventors:

Yin Qian, Milpitas, CA (US);

Hsin-Chih Tai, San Jose, CA (US);

Tiejun Dai, Santa Clara, CA (US);

Duli Mao, Sunnyvale, CA (US);

Cunyu Yang, Milpitas, CA (US);

Howard E. Rhodes, Nokomis, FL (US);

Assignee:

OmniVision Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/58 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1469 (2013.01); H01L 23/585 (2013.01); H01L 24/94 (2013.01); H01L 27/14618 (2013.01); H01L 27/14636 (2013.01); H01L 27/14683 (2013.01); H01L 27/14689 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/94 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/12043 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/37001 (2013.01);
Abstract

An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.


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