The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Feb. 18, 2015
Applicant:

Hisanori Ihara, Seongnam-si, KR;

Inventor:

Hisanori Ihara, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 31/036 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14605 (2013.01); H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14614 (2013.01); H01L 27/14638 (2013.01); H01L 27/14689 (2013.01); H01L 27/14627 (2013.01);
Abstract

Image sensors are provided including a substrate defining a plurality of pixel regions, the substrate having a first surface and a second surface opposite the first surface. The second surface of the substrate is configured to receive light incident thereon and the substrate defines a deep trench extending from the second surface of the substrate toward the first surface substrate and separating the plurality of pixel regions from each other. In each of the plurality of pixel regions of the substrate, a photoelectric conversion region is provided. A gate electrode is provided on the photoelectric conversion region and a negative fixed charge layer covering the second surface of the substrate and at least a portion of a sidewall of the deep trench is also provided. The image sensors further include a shallow device isolation layer on the first surface of the substrate. The shallow device isolation layer defines an active region in each of the pixel regions and the negative fixed charge layer contacts the shallow device isolation layer.


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