The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2016
Filed:
Dec. 20, 2012
Applicant:
Panasonic Corporation, Osaka, JP;
Inventors:
Assignee:
Panasonic Corporation, Osaka, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 27/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 23/522 (2013.01); H01L 27/0207 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A first dummy via pattern having high density is arranged in the vicinity of first and second wirings on a semiconductor device, and a second dummy via pattern having low density is arranged in a distant region from the first and second wirings, with reference to the first dummy via pattern. Accordingly, it is possible to suppress expansion of the file size of layout CAD data due to dummy vias, while complying with a design standard regulated for each semiconductor process, regardless of the presence or absence of vias which connect the first wirings to the second wirings.