The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Oct. 28, 2014
Applicants:

Stmicroelectronics SA, Montrouge, FR;

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Denis Rideau, Grenoble, FR;

Emmanuel Josse, La Motte Servolex, FR;

Olivier Nier, Varces, FR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 21/84 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76283 (2013.01); H01L 21/02356 (2013.01); H01L 21/84 (2013.01); H01L 29/7846 (2013.01); H01L 29/7847 (2013.01); H01L 21/324 (2013.01);
Abstract

One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.


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