The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Mar. 25, 2015
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Young Ho Lee, Gyeonggi-do, KR;

Keum Bum Lee, Gyeonggi-do, KR;

Min Yong Lee, Gyeonggi-do, KR;

Hyung Suk Lee, Gyeonggi-do, KR;

Seung Beom Baek, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01); H01L 21/02 (2006.01); H01L 29/36 (2006.01); H01L 29/66 (2006.01); H01L 29/868 (2006.01); H01L 27/24 (2006.01); H01L 21/22 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0257 (2013.01); H01L 21/02373 (2013.01); H01L 21/02378 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 27/2409 (2013.01); H01L 29/36 (2013.01); H01L 29/66121 (2013.01); H01L 29/868 (2013.01); H01L 21/2205 (2013.01); H01L 29/161 (2013.01);
Abstract

An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.


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