The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Dec. 20, 2013
Applicant:

Netapp, Inc., Sunnyvale, CA (US);

Inventors:

Joshua Silberman, Redwood City, CA (US);

George Totolos, Cranberry Township, PA (US);

Richard Strong, Pittsburgh, PA (US);

Assignee:

NetApp, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/04 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G06F 11/1048 (2013.01); G11C 29/44 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Examples are disclosed for assessing pass/fail status of non-volatile memory. In some examples, information may be received to indicate a block having memory pages associated with non-volatile memory cells. The information may indicate at least some of the memory pages have bit errors in excess of an error correction code (ECC) ability to correct. For these examples, the block may be selected for read testing. Read testing may include programming the memory pages with a known pattern and waiting a period of time. Following the period of time each memory page may be read and if a resulting pattern read matches the known pattern programmed to each memory page, the memory page passes. The block may be taken offline if the number of passing memory pages is below a pass threshold number. Other examples are described and claimed.


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