The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Jul. 17, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Haksoo Yu, Seongman-si, KR;

Dae-Hyun Kim, Hwaseong-si, KR;

Uksong Kang, Seongnam-si, KR;

Chulwoo Park, Yongin-si, KR;

Joosun Choi, Yongin-si, KR;

Hyojin Choi, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 7/10 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G11C 11/403 (2006.01); G11C 11/406 (2006.01); G11C 29/00 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G06F 12/0207 (2013.01); G06F 12/0223 (2013.01); G06F 12/0638 (2013.01); G11C 11/403 (2013.01); G11C 11/40622 (2013.01); G11C 29/783 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A semiconductor memory cell array is provided which includes a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed. The first and second memory cell array areas are accessed by addressing of a DRAM controller.


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