The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Nov. 08, 2013
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, CN;

Inventors:

Fan Li, Beijing, CN;

Hongwei Li, Beijing, CN;

Tianma Li, Beijing, CN;

Xiaomei Huang, Beijing, CN;

Youqiang Lu, Beijing, CN;

Jing Wang, Beijing, CN;

Yun Qiu, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G09G 3/36 (2006.01); G02F 1/133 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3696 (2013.01); G02F 1/13306 (2013.01); G09G 3/3648 (2013.01); G09G 2300/0876 (2013.01); G09G 2320/103 (2013.01); G09G 2330/021 (2013.01); G09G 2340/0435 (2013.01);
Abstract

The present invention discloses array substrate, display device and method for controlling refresh rate of an array substrate. The array substrate includes; a plurality of pixel structures each including gate line, data line, common electrode line, first switching element at intersection of the gate line and the data line, pixel electrode, second switching element, and first transparent electrode. Gate, source and drain of the first switching element are connected to the gate line, the date line and the pixel electrode, respectively. Gate, source and drain of the second switching element are connected to second switching controlling line, common electrode signal terminal and the first transparent electrode, respectively. A first storage capacitance is formed between the pixel electrode and the common electrode line and/or between the pixel electrode and the gate line, and a second storage capacitance is formed between the pixel electrode and the first transparent electrode.


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