The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Jul. 23, 2013
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Ian Bratt, San Jose, CA (US);

Mladen Wilder, Cambridge, GB;

Ole Henrik Jahren, Trondheim, NO;

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0855 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01);
Abstract

A coherent memory system includes a plurality of level 1 cache memoriesconnected via interconnect circuitryto a level 2 cache memory. Coherency control circuitrymanages coherency between lines of data. Evict messages from the level 1 cache memories to the coherency control circuitryare sent via the read address channel AR. Read messages are also sent via the read address channel AR. The read address channel AR is configured such that a read message may not be reordered relative to an evict message. The coherency control circuitryis configured such that a read message will not be processed ahead of an evict message. The level 1 cache memoriesdo not track in-flight evict messages. No acknowledgement of an evict message is sent from the coherency control circuitryback to the level 1 cache memory


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