The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Dec. 22, 2014
Applicant:

Telefonaktiebolaget L M Ericsson (Publ), Stockholm, SE;

Inventors:

Andreas Olsson, Stockholm, SE;

Håkan Axelsson, Linköping, SE;

John Walter Diachina, Garner, NC (US);

Peter Östrup, Linköping, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04W 72/04 (2009.01); H04W 74/08 (2009.01); H04W 72/14 (2009.01); H04W 74/00 (2009.01); H04W 72/12 (2009.01);
U.S. Cl.
CPC ...
H04W 72/0446 (2013.01); H04W 72/0413 (2013.01); H04W 72/14 (2013.01); H04W 74/008 (2013.01); H04W 74/0833 (2013.01); H04W 72/1284 (2013.01); H04W 74/08 (2013.01);
Abstract

The present invention is a method and system adapted to facilitate, between a mobile station (MS) and network, an indication of support for reduced time transmission interval (RTTI). The MS can provide a base station system (BSS) with an indication of its multislot capability within an access burst sent at the start of a contention based access. In another aspect, the MS can indicate support for a new Immediate Assignment message as the conventional Immediate Assignment message can only assign single timeslots. The present invention enables the Radio Access Network (RAN) to assign RTTI and more than one timeslot for GPRS/EDGE temporary block flows (TBFs) during an Access Grant Channel (AGCH) assignment. The method of the present invention can be implemented in a computer program product or distributed software adapted to be loaded into at least one or a plurality of memory locations and executed by at least one or a plurality of respective computer processors.


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