The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Mar. 24, 2015
Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Tomohiko Ebata, Kanagawa, JP;

Takuji Aso, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/10 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1076 (2013.01); H03M 1/12 (2013.01); H03M 1/1225 (2013.01);
Abstract

The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP, MP, and MPc, and first, second, and third NMOS transistors MN, MN, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MNand the second PMOS transistor MPare turned on, and the first NMOS transistor MN, the first PMOS transistor MP, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.


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