The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Jan. 07, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventor:

Jun-Suk Kim, Goyang-Si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66818 (2013.01); H01L 21/30604 (2013.01); H01L 21/823412 (2013.01); H01L 21/823425 (2013.01); H01L 21/823431 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01); H01L 29/165 (2013.01);
Abstract

Provided are methods of forming a semiconductor device having an embedded stressor. The method includes forming a fin active area on a substrate. A gate structure configured to cross the fin active area and cover a side surface of the fin active area, and a gate spacer on a sidewall of the gate structure are formed. Preliminary trenches are formed in the fin active area adjacent to both sides of the gate structure using an anisotropic etching process. An etching select area is formed by oxidizing the fin active area exposed to the preliminary trenches. Trenches are formed by removing the etching select area. A stressor is formed in each of the trenches.


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