The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Feb. 11, 2015
Applicant:

National Central University, Taoyuan, TW;

Inventors:

Pei-Wen Li, Taoyuan, TW;

Wei-Ting Lai, New Taipei, TW;

Ting-Chia Hsu, Taoyuan, TW;

Kuo-Ching Yang, Nantou County, TW;

Po-Hsiang Liao, New Taipei, TW;

Thomas George, La Canada, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/28114 (2013.01); H01L 21/3065 (2013.01); H01L 29/4236 (2013.01); H01L 29/66613 (2013.01); H01L 21/02255 (2013.01);
Abstract

A method for manufacturing a metal-oxide-semiconductor (MOS) gate stack structure in an insta-MOS field-effect-transistor (i-MOSFET) includes the following steps of: forming a silicon nitride layer over a silicon substrate; forming a nanopillar structure including a silicon-germanium alloy layer in contact with the silicon nitride layer; and performing a thermal oxidation process on the nanopillar structure to cause germanium atoms in the silicon-germanium alloy layer to penetrate the underneath silicon nitride layer to form a silicon-germanium shell layer in contact with the silicon substrate and a germanium nanosphere located over the silicon germanium shell layer, and to form a separating layer between the silicon-germanium shell layer and the germanium nanosphere by oxidizing silicon atoms from the silicon nitride layer or the silicon substrate, thereby forming a germanium/silicon dioxide/silicon-germanium i-MOS gate stack structure capable of solving interfacial issues between silicon and germanium and between germanium and the gate dielectric.


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