The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2016
Filed:
Nov. 08, 2013
Applicant:
Brewer Science Inc., Rolla, MO (US);
Inventors:
Assignee:
Brewer Science Inc., Rolla, MO (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 51/00 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); B81C 1/00 (2006.01); B81C 99/00 (2010.01); G03F 1/50 (2012.01); G03F 7/00 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0676 (2013.01); B81C 1/00111 (2013.01); B81C 99/008 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); G03F 1/50 (2013.01); G03F 7/0035 (2013.01); H01L 21/0259 (2013.01); H01L 21/02606 (2013.01); H01L 29/0665 (2013.01); H01L 29/0669 (2013.01); H01L 51/0048 (2013.01);
Abstract
Manufacturing-friendly and scalable methods for the production of silicon micro- and nanostructures, including silicon nanotubes, are described. The inventive methods utilize conventional integrated circuit and MEMS manufacturing processes, including spin-coating, photolithography, wet and dry silicon etching, and photoassisted electrochemical etch processes. The invention also provides a novel mask, for maximizing the number of tubes obtained per surface area unit of the silicon substrate on which the tubes are built. The resulting tubes have thick and straight outer walls, as well as high aspect ratios.