The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Nov. 11, 2014
Applicants:

James M. Holden, San Jose, CA (US);

Brad Eaton, Menlo Park, CA (US);

Aparna Iyer, Sunnyvale, CA (US);

Ajay Kumar, Cupertino, CA (US);

Inventors:

James M. Holden, San Jose, CA (US);

Brad Eaton, Menlo Park, CA (US);

Aparna Iyer, Sunnyvale, CA (US);

Ajay Kumar, Cupertino, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/66 (2006.01); B23Q 3/18 (2006.01); H01L 21/304 (2006.01); H01L 21/683 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); B23Q 3/18 (2013.01); H01L 21/308 (2013.01); H01L 21/3043 (2013.01); H01L 21/3065 (2013.01); H01L 21/67207 (2013.01); H01L 21/6836 (2013.01); H01L 22/26 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68377 (2013.01);
Abstract

Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a carrier for supporting a wafer or substrate in an etch process includes a frame having a perimeter surrounding an inner opening. The carrier also includes a tape coupled to the frame and disposed below the inner opening of the frame, the tape comprising an etch stop layer disposed above a support layer.


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