The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Dec. 21, 2005
Applicants:

Hideki Arakawa, Kawasaki, JP;

Takuo Ito, Kawasaki, JP;

Inventors:

Hideki Arakawa, Kawasaki, JP;

Takuo Ito, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/308 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3088 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/3086 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01);
Abstract

There is provided a method of fabricating a semiconductor device including forming a first film on a base layer, forming a first mask pattern on the first film, the first mask pattern having mask portions arranged at a given pitch, forming first sidewall films on sidewalls of the first mask pattern by etchback of a deposited second film, removing the first mask pattern, and forming a second mask pattern composed of the first sidewall films and second sidewall films defined by etchback of a deposited third film. It is possible to form a stripe pattern with the line width and the line space thereof having the same sizes and at a pitch the same as the minimum process size determined by the photolithographic performance, thereby enabling fabrication of a semiconductor device with a high degree of integration.


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