The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2016
Filed:
Jun. 19, 2013
Nvidia Corporation, Santa Clara, CA (US);
Vikas Agrawal, San Jose, CA (US);
Shrivathsa Bhargavravichandran, San Jose, CA (US);
Binh Pham, San Jose, CA (US);
Jay Chen, Sunnyvale, CA (US);
Sridhar Krishnamurthy, Santa Clara, CA (US);
Umang Shah, San Jose, CA (US);
Chi Keung Lee, San Jose, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.