The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Jul. 06, 2010
Applicant:

Larry J. Thayer, Ft. Collins, CO (US);

Inventor:

Larry J. Thayer, Ft. Collins, CO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 11/10 (2006.01); H04L 25/14 (2006.01); G06F 13/16 (2006.01); H04L 1/24 (2006.01); H04B 10/40 (2013.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4295 (2013.01); G06F 13/1673 (2013.01); G06F 13/1684 (2013.01); H04B 10/40 (2013.01); H04L 1/0001 (2013.01); H04L 1/242 (2013.01); H04L 25/14 (2013.01); G06F 11/1004 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

A disclosed example bit error rate reduction buffer comprises a data recovery circuit including differential bit pair inputs and differential bit pair outputs, a CRC circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator, and a serializer including differential bit pair inputs and differential bit pair outputs. The differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit, the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer, the differential bit pair inputs of the data recovery circuit to be driven by a first HSS link, the different bit pair outputs of the serializer to drive a second HSS link; and the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit.


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