The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Nov. 18, 2011
Applicants:

Stéphane Le Tual, Saint-Egrève, FR;

Pratap Singh, Varanasi, IN;

Inventors:

Stéphane Le Tual, Saint-Egrève, FR;

Pratap Singh, Varanasi, IN;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/423 (2013.01);
Abstract

The invention concerns a circuit comprising: a first circuit block () adapted to receive a first clock signal (CLK) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block () adapted to receive a second clock signal (CLK) and to provide a second output data signal at a time determined by said second clock signal; a clock bus () coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit () coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.


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