The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Nov. 13, 2014
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Siddharth Devarajan, Arlington, MA (US);

Lawrence A. Singer, Wenham, MA (US);

Prawal Man Shrestha, Somerville, MA (US);

Pingli Huang, Santa Clara, CA (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/06 (2006.01); H03M 1/08 (2006.01); H03M 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/121 (2013.01); H03M 1/0604 (2013.01); H03M 1/0607 (2013.01); H03M 1/0609 (2013.01); H03M 1/0612 (2013.01); H03M 1/0836 (2013.01); H03M 1/124 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01);
Abstract

A time-interleaved analog-to-digital converter (ADC) uses M sub-analog-to-digital converters (sub-ADCs) to, according to a sequence, sample an analog input signal to produce digital outputs. When the M sub-ADCs are interleaved, the digital outputs exhibit mismatch errors between the M sub-ADCs due to mismatches between the sub-ADCs. A more second order subtle effect is that the mismatch error for a particular digital output from a particular ADC, due to internal coupling or other such interaction and effects between the M sub-ADCs, can vary depending on which sub-ADC(s) were used before and/or after the particular sub-ADC. If M sub-ADCs are time-interleaved randomly, the mismatches between the M sub-ADCs become a function of the sub-ADC selection pattern in the sequence. The present disclosure describes mechanisms for measuring and reducing these order-dependent mismatches to achieve high dynamic range performance in the time-interleaved ADC.


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