The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Mar. 28, 2014
Applicant:

Fairchild Semiconductor Corporation, San Jose, CA (US);

Inventors:

Tyler Daigle, Portland, ME (US);

Julie Lynn Stultz, Scarborough, ME (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/56 (2006.01); H03K 17/06 (2006.01); H02J 7/00 (2006.01);
U.S. Cl.
CPC ...
H03K 17/063 (2013.01); H02J 7/0029 (2013.01); H03K 2217/0018 (2013.01); H03K 2217/0054 (2013.01);
Abstract

An apparatus comprises at least one transistor configured as analog switch, a well biasing circuit configured to provide a dynamic electrical bias to a bulk region of the at least one transistor, and a comparator circuit in electrical communication with the well biasing circuit and the transistor. The comparator circuit is configured to detect a first operating condition of the transistor and a second operating condition of the transistor. The well biasing circuit is configured to apply a first electrical bias to the bulk region of a transistor when the first operating condition is detected and apply a second electrical bias to the bulk region of the transistor when the second operating condition is detected, and wherein the comparator is configured to apply hysteresis to detection of the first and second operating conditions.


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