The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2016
Filed:
Jul. 22, 2014
Freescale Semiconductor, Inc., Austin, TX (US);
Robert L. Maziasz, Austin, TX (US);
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
Hierarchical layout synthesis of complex cells. In some embodiments, a method may include partitioning a cell into a plurality of subcells, where the cell represents a set of electronic components in an integrated circuit; identifying, among the plurality of subcells, a most complex subcell; synthesizing a layout of the most complex subcell for each of one or more side-port configurations; selecting a side-port configuration based upon the layout of the most complex subcell; and synthesizing a layout of one or more of the plurality of subcells neighboring the most complex subcell by propagating one or more constraints associated with the selected side-port configuration.