The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Jan. 23, 2015
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventors:

Mitsuhiro Matsumoto, Kyoto, JP;

Yoichi Takagi, Kyoto, JP;

Tadashi Nomura, Kyoto, JP;

Akihiko Kamada, Kyoto, JP;

Nobuaki Ogawa, Kyoto, JP;

Kensei Nishida, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 25/16 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 25/165 (2013.01); H01L 23/3135 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 24/17 (2013.01); H01L 25/0652 (2013.01); H01L 25/16 (2013.01); H01L 23/3128 (2013.01); H01L 23/50 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19106 (2013.01);
Abstract

A low profile module is provided that has a high functionality achieved by increasing the component mounting density. In spite of achieving high functionality in a moduleby respectively mounting components such as a semiconductor substrateand chip componentson the two main surfacesandof a wiring substrate, the low-profile modulecan be provided which has a high functionality as a result of increasing its component mounting density by forming a thickness Ha of a first component layerformed by mounting only the semiconductor substrateface down on one main surfaceof the wiring substrateso as to be smaller than the thickness of a second component layerformed by mounting a plurality of chip componentson the other main surfaceof the wiring substrate


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