The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2016
Filed:
Jul. 20, 2012
Applicant:
Laurent-luc Chapelon, Domene, FR;
Inventor:
Laurent-Luc Chapelon, Domene, FR;
Assignee:
STMicroelectronics (Crolles 2) SAS, Crolles, FR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 21/6835 (2013.01); H01L 23/3192 (2013.01); H01L 23/481 (2013.01); H01L 24/11 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/1301 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13147 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/15311 (2013.01);
Abstract
An electronic chip including a semiconductor substrate () covered with an insulating layer () including metal interconnection levels () and interconnection pillars () connected to said metal interconnection levels (), said pillars () forming regions () protruding from the upper surface of said insulating layer () and capable of forming an electric contact, wherein said pillars () have a built-in portion () in a housing formed across the thickness of at least said insulating layer ().