The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Mar. 13, 2013
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Nam-Yeal Lee, Gyeonggi-do, KR;

Seung-Jin Yeom, Gyeonggi-do, KR;

Sung-Won Lim, Gyeonggi-do, KR;

Seung-Hee Hong, Gyeonggi-do, KR;

Hyo-Seok Lee, Gyeonggi-do, KR;

Dong-Seok Kim, Gyeonggi-do, KR;

Seung-Bum Kim, Gyeonggi-do, KR;

Sei-Jin Kim, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 27/108 (2006.01); H01L 21/764 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/764 (2013.01); H01L 21/76224 (2013.01); H01L 21/76831 (2013.01); H01L 21/76897 (2013.01); H01L 23/48 (2013.01); H01L 27/10855 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 21/76847 (2013.01); H01L 2924/0002 (2013.01);
Abstract

This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.


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