The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Jun. 18, 2014
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Jung Il Cho, Icheon-si, KR;

Jong Moo Choi, Cheongju-si, KR;

Eun Joo Jung, Icheon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/764 (2006.01); H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 27/115 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/764 (2013.01); H01L 21/022 (2013.01); H01L 21/02203 (2013.01); H01L 21/28202 (2013.01); H01L 21/28273 (2013.01); H01L 21/31116 (2013.01); H01L 21/762 (2013.01); H01L 27/11521 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 29/518 (2013.01);
Abstract

A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.


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