The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Jun. 25, 2012
Applicants:

Yuhichiroh Murakami, Osaka, JP;

Shige Furuta, Osaka, JP;

Makoto Yokoyama, Osaka, JP;

Seijirou Gyouten, Osaka, JP;

Inventors:

Yuhichiroh Murakami, Osaka, JP;

Shige Furuta, Osaka, JP;

Makoto Yokoyama, Osaka, JP;

Seijirou Gyouten, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3648 (2013.01); G09G 3/3655 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G09G 3/3659 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0219 (2013.01);
Abstract

A retention circuit () corresponding to each stage of a shift register is configured such that, when SROUT(k−1) is active, an input terminal of an inverter (INV) and an output terminal of an inverter (INV) are electrically connected to each other and an output terminal of the inverter (INV) and an input terminal of the inverter (INV) are connected to each other. This makes it possible to reduce a circuit scale of a display driving circuit without causing any malfunction of the display driving circuit.


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