The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Sep. 30, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Gregory J. Cook, Raleigh, NC (US);

Timothy J. Koprowski, Newburgh, NY (US);

Mary P. Kusko, Hopewell Junction, NY (US);

Cedric Lichtenau, Stuttgart, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/27 (2006.01); G01R 31/3187 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 11/27 (2013.01); G06F 17/50 (2013.01); G01R 31/3187 (2013.01);
Abstract

Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes a computer program product for implementing design-based weighting for LBIST. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units. The integrated circuit layout is incorporated in a device under test.


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